On the VC707 design for the AD-FMCOMMS3-EBZ board - the incoming rx_clk_in rate is directly related to the sampling frequency set correct?
When set to max sampling rate 61.44MZPS then the max rate would be 245.76 MHz correct (looking at UG-570 pg 108), however what I wanted to confirm is as sampling rates decrease, the clk rate would then change to be rx_clk_p/n = 4 x sampling_rate correct?
If one keeps their sampling rate constant, can one rely on the "l_clk" signal ouput of the axi_ad9361 to be reliable and use it for their system clock (or is this bad practice- should use one of the VC707 System Clock via MMCM)?
It appears the axi_ad9361 block puts the rx_clk_in from the FMCOMMS3 board on a bufg and outputs it as l_clk which I'd like to possibly clock other blocks in my system with.
Is clocking the microBlaze / timing specific software (counters) dependant on 100MHz clock or could this 100MHz be slowed down to what minimum value safely?
I ask because my future design will eliminate the DDR3 controller where the 100MHz, and 200MHz example design clocks originate from currently.. and I'll be running uB on BRAM.