Is there a recommended location/method within the AD-FMCOMMS3-EBZ VC707 example design to modify to get the rx data into one's own processing chain of custom HDL blocks? And where to put tx data into the stream to be sent out?
I ask because:
* would be nice to build off example design
* since I Q data size is 12 bits, the data paths that are 16 bits for i, and 16 bits of q, for this application only bits 11 downto 0 are used, 12 bits correct, and MSBs 15 downto 12 -- 5 bits are just unused values correct?
* looking at rx data path I saw a few options:
1- I could write my own block for reading incoming rx_clk,frame, and data straight off the pins, before the axi_ad9361... or
2- If I branched the RX data leaving axi_ad9361 block (adc_data_i0, adc_valid_i0, adc_dataq0, adc_valid_q0) -- I was worried about IQ samples must be aligned but here I have 2 different valids- Are these valids at different times? How could I tell which valid I goes with which valid Q so I'm not off in my pairs of IQ for samples?
3- I could take the output of the sys_wfifo_0, sys_wfifo1 for I Q data and just read them at the same time when both aren't empty, but again concern about the IQ pairs lining up since they went in different fifo's with different valids...
with tx data, if I have my 12 bit samples to put on the stream to transmit - is the best method to feed these through the axi_ad9361 block and put them on the dac_data_i/q0 pins? How does it know when is best to write these, I don't see a valid?
Otherwise it looks like I'd have to send my data values through the axibus via the microblaze and I don't want to do this, would need embedded code, axi i/o from where my data originates from, etc? I'm not well versed in the embedded, axi and microblaze area yet...