Is it feasible to move the VC707 AD-FMCOMMS3-EBZ Microblaze configuration from using the DDR3 SODIMM 1 GB RAM space to using on FPGA Block RAM BRAM?
Has anyone done this to your knowledge? If so - any current instructions / examples to make this change?
How many Block Ram's would I expect to take up, how large of a BRAM space must I allocate?
I figure it's feasible, the VC707 Virtex7 XC7VX485T appears to have max 37,080Kb of BRAM and the compiled no-OS .elf appears to give:
text data bss dec hex filename
192100 3804 1050184 1246088 130388 sw.elf
If I understand correctly it may take 1 of 4 MBytes of BRAM, 1/4th of the FPGA total to run the no-OS on BRAM?
What/how should/could I cut down if anything to get the embedded code size requirements smaller? My application is fairly simple where I won't use any TDD application, just using 1 of the 2 channels for constant Rx and Tx channels, no HDMI stuff. Is there a recommended method to eliminate things from the embedded and example HDL design?
Within the HDL realm, I tried removing HDMI blocks in the bd design through the tcl files, and it's been a pain where things won't build or validate without ports connected, I wonder if there's a way in tcl to just terminate ports, etc..