I am using AD9248 , High Speed ADC in my Design ....... I am interfacing it to the Spartan 6 FPGA.
I want to know ,when i have to read the the output parallel data.
There is input Clock CLK_A for channel in A ... and Output Enable OEB_A .
1. Will reading the output data be based on the input Clock CLK_A by giving the same clock to both ADC and FPGA , and OEB_A pulled down to enable the O/P always ?
2, What if clock CLK_A for ADC is generated form FPGA itself ?
In Schematic i have connected input clock CLK_A to both ADC and FPGA , and OEB_A to GND.
HAL , Hyderabad