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Mapping I and Q samples to dac_ddata_1 and dac_ddata_0 in fmcomms1

Question asked by Jetmiri on Mar 11, 2015
Latest reply on Apr 2, 2015 by rejeesh

Hi all,

 

I just want to ask why we are doubling the I and Q samples in hdl/system_top.v at master · analogdevicesinc/hdl · GitHub . I have an output of 4 I samples and 4 Q samples 16 bits each. Can I map each I and Q sample to dac_ddata_1 and dac_ddata_0 respectively!? So i will have 4 I samples in dac_ddata_1 and 4 Q samples dac_ddata_0 each clock.

 

Regards,

Jet.

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