I am developing the zynq with ad9364 using the Linux user space driver. I use the fpga reference design that is downloaded from github and the example code running in SDK. I changed the reference_clk_rate to 20MHz and set two_rx_two_tx_mode_enable to 0. However when I am trying to use the adc_capture function, the process get stuck in here (in adc_core.c, in function adc_capture)
/* Wait until the current transfer is completed. */
while(reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT));
It since the EOT from adc dma in the HDL project is not generated, can anyone give me a clue? I've use chipscope and found there were active adc data flowing and been written to the DDR through the HP_axi interface. Apart from the different I made as state at the beginning of this post, I am using the UIO which seems to work without problem although I think it doesn't cause the this problem.
Thanks in advance.