I am in the process of qualifying the AD5522 for use into a new product.
I use the evaluation board EVAL-AD55222EBDZ (whose accompanying PC software is rather , but this is another question) and I am into trouble.
Here are the test conditions :
- AVDD = +12 V
- AVSS = -12 V
- DVCC = +5 V
- VREF = +5 V
- FVMI mode, current range ±2 mA
- OFFSET DAC = A492hex
- MEASOUT = VSENSE
- AGND connected to DGND
- DUTGND2 and DUTGND are connected to AGND
- DUTGND/channel is disabled
- GUARD is disabled
- MEASVH2 connected to FOH2
- current clamped to ±440 µA (CLL X1 = 7000hex, CLH X1 = 9000hex)
- Voltage set to +4 V
- MEASOUT gain = 1
- MEASVH2, FOH2 voltage swept by HP Agilent Keysight's B2901A SMU from -10 to +10 V
- MEASOUT2 is observed on an oscilloscope channel.
What I see is that the voltage at MEASOUT2 follows the voltage on MEASVH2, but will not go below -5 V.
If I change the Voltage setting to +6 V, MEASOUT2 will not go below -3 V, etc : there seem to be a maximum difference of 9 V between the Voltage setting and MEASOUT2 (so if Voltage is set below -3V, the restriction phenomenon will not show).
On the positive side, there is no such capping effet.
With MEASOUT gain = 0.2 the same voltage restriction seem to exist but (of course) at a different scale.
The phenomenon seems unrelated to AVSS, the current range, the current clamping, the Guard setting, the DUTGND/channel setting, the 10k resistor setting. It is slightly (not proportionally) related to AVDD.
I did not found anything on this in the datasheet. Any hint would be appreciated