I'm trying to implement some flow control on the AD9361 DAC DMA in the HDL reference design. I have my own module that processes data that is output by the DAC DMA. Essentially, I need a way to hold the the DAC DMA data for 4 clock cycles while my module does some data processing. I also cannot afford to drop any packets.
I noted that the DAC DMA module (based on the axi_dmac code) has a "fifo_rd_en" input. If I set this signal low, would the DMA output be held accordingly?
Also, I noticed the DAC DMA doesn't seem to have any fifo in it. The input data is connected directly to the output data. Would holding the data result in packets being dropped?