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Question about Blackfin SPI Port  with hardware driven slave selects

Question asked by KWM on Nov 19, 2010
Latest reply on Nov 22, 2010 by KWM

Hi:

  I'm new to Blackfin, using an EZ-DSP Blackfin 506 Kit and have run into a small problem with the Hardware Driven Slave select, using Core derived transfers.  I have configured SPI0 as a master, and have two devices that I would like to select between by using the SPI0_FLG register.  Each slave select works correctly when selected, and the selected slave_select goes active low during the transmission.  However, the deselected slave select stays low, or in the asserted state.  I was expecting the deselected slave_select to be high.  From the hardware manual it appears that the PORTF_MUX , PORTF_FER, and PORTF_CTL need to be set up, and then writes to the SPI0_FLG register select which slave select goes active.

 

Here are the two routines I use, each is called prior to a transmission on the desired device :  PF14 and PF15 are the pins being probed

void SPI_IF_Init(void)                    // Ths routine Initializes the SPI0 for Slave_Select_3

{

*pPORTF_MUX |= 0x0050;    // Force SPI Function ( 1st Alternate ) for PF10 - PF14
*pSPI0_CTL         &= ~( TIMOD );                                 /* Clear 2bit Timer Mode Field */
*pSPI0_CTL         |=     ( SPE | MSTR | SIZE | PSSE | GM | TDBR_CORE);
*pSPI0_CTL         &= ~( WOM | CPOL | CPHA | LSBF | EMISO | SZ );
*pSPI0_FLG           |=  (FLS3);                                    /* Enable SPI0_Slave_Select_3  */
*pSPI0_FLG         &= ~(FLS2);                                    /* Disable SPI0_Slave_Select_2  */
}

 

void SPI_SYN_Init(void)                    // Ths routine Initializes the SPI0 for Slave_Select_2

{

*pPORTF_MUX |= 0x0050;    // Force SPI Function ( 1st Alternate ) for PF10 - PF14
*pSPI0_CTL         &= ~( TIMOD );                                 /* Clear 2bit Timer Mode Field */
*pSPI0_CTL         |=     ( SPE | MSTR | SIZE | PSSE | GM | TDBR_CORE);
*pSPI0_CTL         &= ~( WOM | CPOL | CPHA | LSBF | EMISO | SZ );
*pSPI0_FLG           |=  (FLS2);                                    /* Enable SPI0_Slave_Select_2  */
*pSPI0_FLG         &= ~(FLS3);                                    /* Disable SPI0_Slave_Select_3  */
}

 

After either routine above is called, a simple write to the SPI0_TDBR starts the transfer.  The SPI Hardware selects and activates the correct selected Slave Select, but leaves the other low (asserted ), when I think it should be high (deasserted).   There are no other external connections to these pins.

 

Am I missing something fundamental, is there some order that the SPI registers need to be loaded?   I also have a question about the role of the "CPHA" bit on page 18-38 of  rev .2 of the Blackfin 504 / 506 the manua  - here is a manual excerpt from page 1-38l:

 

"  If CPHA = 0, the SPI hardware sets the output value and the FLGx

bits are ignored. The SPI protocol requires that the slave select be

deasserted between transferred words. In this case, the SPI hardware

controls the pins. For example, to use the slave select function

on a port pin to which it is mapped, it is only necessary to set the

appropriate

FLS bit in SPI_FLG. It is not necessary to write to an FLG

bit, because the SPI hardware automatically drives the port pin."

 

CPHA is the Clock Phase bit and PSSE is the Slave Select  is this a typo in the manual.

 

Any help on this would be greatly appreciated, also if there is a bug, can someone show the correct SPI settings / code to use the FLG bits to

manually toggle the Slave Selects through the SPI0_FLG Register?

 

Thanks for any assistance on this!

KWM

 

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