The AD6676 data sheet only mentions the issue of clock jitter in this statement "...clock jitter and phase noise must always be a concern in selecting the clock source." In a conventional pipelined ADC, the maximum SNR for a given clock jitter is inversely proportional to the input signal frequency and it is simple to estimate. I have read in the academic literature that the sigma delta converter STF is directly affected by clock jitter, that is, there is no suppression of jitter noise like there is for quantization noise in the i.f. passband. Should I continue to use the relatively simple way to estimate maximum SNR as in MT-008 Eq. 1, or is there a more accurate way to estimate maximum SNR (or an equivalent figure of merit) due to clock jitter in the AD6676?
A related question is if I know the phase noise performance of the clock source, do I need to use a broadband calculation of jitter or can it be a narrower bandwidth such as 12 kHz to 20 MHz assuming that I have selected AD6676 IF BW = 20 MHz? ADIsimClk provides several possible jitter values for the AD9525 clock generator that I am considering as a 3.2 GHz clock source, broadband jitter being the largest.