AnsweredAssumed Answered

Trouble with activating SPORT0 secondary side, ADSP-BF561 EZ-Kit Lite

Question asked by chris_k. on Mar 6, 2015
Latest reply on Mar 10, 2015 by chris_k.

Hello!

 

I'm actually connecting two Cirrus Logic CS42448 audio codecs to the SPORT0 interface of an ADSP-BF561 EZ-Kit Lite.

The TDM-connection to the codec connected to the SPORT0 pirmary side is working fine and i'm having trouble activating the secondary side.

 

The code below shows my initialization and activation of SPORT0, DMA and corresponding interrupt. The CS42448 codec works with 8 channels of 32 Bit data in TDM datastreams for transmit and receive.

The changes i made for activating primary and secondary side are commented out and marked by <--------------------------.

I also changed the size from the DMA receive and transmit arrays (iRxBuffer1, iTxBuffer1) from 8 elements to 16 elements.

 

Activating the secondary-side-changes, leads to a behaviour i actually can't explain to myself.

Without the secondary side, the interrupt service routine (Sport0_RX_ISR) gets executed with a frequency of approximately 44100Hz, what's fine.

When i'm activating primary and secondary side, the interrupt service routine get's executed with approximately 1,8MHz. I'm not getting any valid input/output data from or to the codecs and it seems like the quick interrupt calls slow down all code outside the interrupt service routine dramatically .

 

Can anyone tell me what i'm making wrong?

 

 

Thank's in advance,

 

chris

 

 

/*******************/

/* Init SPORT0 */

/*******************/

 

//SPORT0 serial clock configuration 

*pSPORT0_TCLKDIV = 0x0003;

*pSPORT0_RCLKDIV = 0x0003;

 

//SPORT0 frame sync configuration

*pSPORT0_TFSDIV = 0x00FF;

*pSPORT0_RFSDIV = 0x00FF;

 

//SPORT0 receive configuration

*pSPORT0_RCR1 = 0x6602;

*pSPORT0_RCR2 = 0x001F; //secondary side disabled

//*pSPORT0_RCR2 = 0x011F; //secondary side enabled <--------------------------

 

//SPORT0 transmit configuration

*pSPORT0_TCR1 = 0x6602;

*pSPORT0_TCR2 = 0x001F; //secondary side disabled

//*pSPORT0_TCR2 = 0x011F; //secondary side enabled <--------------------------

 

//enable MCM 8 receive channels

*pSPORT0_MRCS0 = 0x000000FF;

*pSPORT0_MRCS1 = 0x00000000;

*pSPORT0_MRCS2 = 0x00000000;

*pSPORT0_MRCS3 = 0x00000000;

 

//enable MCM 8 transmit channels

*pSPORT0_MTCS0 = 0x000000FF;

*pSPORT0_MTCS1 = 0x00000000;

*pSPORT0_MTCS2 = 0x00000000;

*pSPORT0_MTCS3 = 0x00000000;

 

//set MCM configuration register and enable MCM mode

*pSPORT0_MCMC1 = 0x0000;

*pSPORT0_MCMC2 = 0x101C;

 

 

/*****************************/

/* Init DMA für SPORT0 */

/*****************************/

 

// Set up DMA2 channel 0 to Sport receive

*pDMA2_0_PERIPHERAL_MAP = 0x0000;

// Configure DMA2 channel0

*pDMA2_0_CONFIG = 0x108A; // 32-bit transfers, Interrupt on completion, Autobuffer mode

// Start address of data buffer

*pDMA2_0_START_ADDR = (void *)iRxBuffer1;

// DMA inner loop count

*pDMA2_0_X_COUNT = 8; //secondary side disabled

//*pDMA2_0_X_COUNT = 16; //secondary side enabled <--------------------------

// Inner loop address increment

*pDMA2_0_X_MODIFY = 4;

 

// Set up DMA2 channel 1 to Sport transmit

*pDMA2_1_PERIPHERAL_MAP = 0x1000;

// Configure DMA2 channel 1

*pDMA2_1_CONFIG = 0x1028; // 32-bit transfers, Autobuffer mode

// Start address of data buffer

*pDMA2_1_START_ADDR = (void *)iTxBuffer1;

// DMA inner loop count

*pDMA2_1_X_COUNT = 8; //secondary side disabled

//*pDMA2_1_X_COUNT = 16; //secondary side enabled <--------------------------

// Inner loop address increment

*pDMA2_1_X_MODIFY = 4;


 

/*****************************/

/* Init SPORT Interrupts */

/*****************************/

 

// assign interrupt channel 23 (DMA2_0) to IVG9

*pSICA_IAR2 = Peripheral_IVG(23,9);

 

// assign ISRs to interrupt vectors

// Sport0 RX ISR -> IVG 9

register_handler(ik_ivg9, Sport0_RX_ISR);

 

// clear pending IVG9 interrupts

*pILAT |= EVT_IVG9;

ssync();

 

// enable Sport0 RX interrupt

*pSICA_IMASK0 |= SIC_MASK(23);

ssync();

 

 

/******************************/

/* Enable DMA SPORT0 */

/******************************/

 

// enable DMAs

*pDMA2_1_CONFIG = (*pDMA2_1_CONFIG | DMAEN);

*pDMA2_0_CONFIG = (*pDMA2_0_CONFIG | DMAEN);

ssync();

 

// enable Sport0 TX and RX

*pSPORT0_TCR1 = (*pSPORT0_TCR1 | TSPEN);

*pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN);

ssync();

Outcomes