I understand that there is Xilinx FPGA Reference Design code available for interleaving the AD9625 ADC data, could you please provide a link to it? Thanks.
For the FMCADC5 design we have a pre-build image, which using a VC707 carrier, its wiki page is a good starting point for bring up. The hdl can be found here.
Moved to FPGA reference designs.
IP core: hdl/library/axi_ad9625 at master · analogdevicesinc/hdl · GitHub
Reference design (FMCADC2) :
The question was "interleaving" - that would be the unreleased ADC5 -- do we have the design posted for that? We showed/announced it at Embedded World, and now need to release what exists.
Retrieving data ...