We are using kintex705 with fmcomms4. We have hdl reference design for Vivado2013.4 with the recent version of NoOS driver.
We are going to design our own PCB with AD9364 IC, which will be interfaced with the FPGA board that contains axi_ad9361 hdl logic.
So, we need to know the setup and hold time imposed by axi_ad9361 hdl logic for rx_frame and rx_data with respect to data_clk.
Thanks in advance.
Vaibhav and Payam