AD9361Tx channel, DDR, an LVDS model, configuration register x010 = 0 c8, 0 x012 = 10,tx spectrum is always wrong,For example, configuration tx frequency of 2 GHz signal, using FPGA to produce 1MHz dds carrier, the spectrum is always three lines, 1999MHz, 2GHz, 2001 MHz, and have some other spur signals, and when configure different HB1, HB2, FIR digital filter, then tx spectrum have some changes , but the main frequency still the same.
so My question is what problem cause this phenomenon?Is Digital interface configuration errors or interface timing problems?
And then I use AD9361 loop test configuration register,0x3F4, Configuration to launch mode,0x3F4=0XC3, the spectrum is right.
and Another problem is How to use the loop test receiving loop, how data interface configuration, OX3F4 or 0 x3f5 registers how to set up? How to operate can be tested?