Can you sugest me a clock spliter chip to drive three PLL REF with one CMOS output tcxo?
Because the REFIN pin on the ADF4xxx PLLs are high impedance (> 10kOhm) you should be able to simply ac-couple the signal into the 3 REFin pins using 3 capacitors. We also have dedicated fan-out buffers like the ADCLK914 (1:4 fan-out) but these are more suited/useful for high frequency signals
But I have to use the OCXO as a 10MHz reference output besides the three PLL ref,the OCXO can't have enough drive to do this.could you give me annother sulotions? I consider using a SN74HCT chip ,but I don't konw what their additive phase noise are.
You can buffer with any OP AMP (AD8061) and her output voltage offset get necessary value manually. That is no needed capacitance at input PLL.
SN74HCT chip is no good solution in CLK chain.
Here is a circuit we have used on some ADI boards to distribute a 10MHz clock like you mentioned.
the idea is to bias the VCTCXO/OCXO output (ac-coupled) at midsupply and then send it through two inverters. The second inverter is necessary to present the falling edge of the VCTXO to the PLL as the PLL samples off the negative edge internally. For a VCTCXO the least noisy edge is the falling one. By only having one inverter, you would be presenting the noisier VCTCXO rising edge to the PLL. I think for the OCXO you could use just one inverter as both edges should be clean. However I think a dual inverter should also be quite cheap.
We routed the REFIN_SHIFT net around the board, and had the pair of inverters at each PLL input, so this idea
could easily be extended to more than 3 PLLs
Rise & Fall Time TCXO about 10 ns at 10 MHz and Propagation delay Time of dual NC7WZ04P6X is only about 1,6 ... 6 ns. May be alignment with. Is it enough?
Rise & Fall Time TCXO about 10 ns at 10 MHz and Propagation delay Time of dual NC7WZ04P6X is only about 1,6 ... 6 ns. May be alignment with.
Is it enough?
I will have a try,thanks!
In our application, I decided to use AD9513, clock buffer/divider. It will support a maximum output frequency of 250MHz CMOS. It also has high impedance I/P.
You should have no trouble driving several PLL reference inputs from a CMOS TCXO. Not sure what frequency you are using and how long the interconnect traces are but I drive a pair of ADF4350 from a single low level emitter output with no problem.
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