The datasheet does not specify a minimum time between the CS~ falling-edge and the following SCLK rising-edge. Has anybody found a value that's small enough to create doubt in the exact position of the data-output stream?
If I'm not mistaken, you are asking for the minimum time from CS falling edge to the SCLK rising edge for the subsequent 15 data bits after the first valid data bit (MSB). Please see figure below.
If so, according to the datasheet (page 9) this would be approximately equal to t16 plus the SCLK low pulse width (t18).
Let me know if I understand your question correctly.
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