Hello, ADI Support Team
Currently, I'm comparing between ADV7930 timing spec and SMPTE-170M standard.
It seems that ADV7930 does not comply with SMPTE-170M.
For the details, please refer to the attachment file.
Best regards, TomY
SMPTE-170 is purely an analog specification. Figure 104 from the data sheet is referring to BT.601 and when the SAV flag occurs. In the same token vain BT.601 does not have a color burst but embeds the color information in the CbCr definition.
Thank you for your answer.
I'd like to clarify the description of H Blanking period between SMPTE-170M and ADV7390 Datasheet.
SMPTE-170M 1.5us + 9.2us=10.7us
ADV7390 Datasheet 4+268+4=276CLK=10.22us(27MHz)
I think that the 10.22us of ADV7930 is not complied with 10.7us of SMPTE-170M.Why is it?
Could you please let me know your opinion for this difference?
You are generating the BT.656 so if you want 289 clocks between the start of the front porch and the end of the back porch, you can do that. I am not sure where Figure 104 came from but the input pixels are controlled by the source, not the ADV7390.
The ADV7390 only uses the input timing with a few pixel clock delays due to internal digital filtering and conversions.
Thank you for your comments.
Sorry, I did not understand your comments.
Please let me clarify again.
What does the "289 clock" which you said refer from? (some kind of standard document? Datasheet?)
Is Figure 104 of datasheet mistake?
The standards I am referring to are ITU BT.656 and SMPTE-170M. Also the book "Video Demystified" is a very good reference on all things video.
The ADV7393 does not change the timing, it only reflects what the input timing is. You can change the SAV and EAV timing at the source. Figure 104 is not a mistake.
Thank you for your reply.
I am referring to both documents of SMPTE-170M and BF656, too.However, I can not find the description of "289 clock" which you said.If possible, could you please capture from your documents and show me?
You mean even if ADV7390 is set to Mode 0 (CCIR-656), ADV7390 does not output SMPTE-170M standard timing?
10.7us * 27MHz = 289 clocks. It's the time shown in the SMPTE-170M standard. It's just a way to relate the analog signal to the sampling rate.
I do not understand yet the difference between 276CLK of Datasheet and 289CLK of SMPTE-170M.
Why is there difference?
Could you please explain a little more about this point?
Sorry for many asking.
The ADV7390 input is based on BT.601 with 720 active video pixel while SMTPE-170M is based on 704 active equivalent pixels. Since the frame rate is the same and with a 13.5MHz clock this will give you different values for the blanking area
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