I am working on an interface from a Xilinx FPGA to the 9364. In the hdl (hdl_2014_r2) from the reference design I believe I have found the block that I will need to port to my FPGA - axi_ad9361_def_if.v. I do not need the full set of HDL for my design, just the interface to the 9364.
Can you tell me how to use this block in LVDS FDD mode? I have been able to simulate the block and ran dac data through it. The closest I have come is to set dac_r1_mode high and clock in the data using dac_valid.
However I have noticed two problems:
1. The tx data appears to be coincident with the falling edge of fb_clk which does not match the timing diagrams in the reference manual. I assume that the data_clk is inverted on our reference design(fmcomms2/zed) using bit 0 of Parallel Port Configuration 1. Is that correct?
2. When I clock two dac data words in, I get three words out on the parallel port bus. The third word is a repeat of the second word, frame signals and all. Is there a way to prevent this?
Thanks for your time.