AnsweredAssumed Answered

To short fall times on tri-level line sync

Question asked by funried on Mar 5, 2015
Latest reply on Mar 10, 2015 by funried

Hi,

I have a problem with the video-sync fall times on a ADV7391 video output.

 

I configure the ADV7391 to generate a 1080p30 Tri-Level signal on output DAC1 and measure the rise and fall times of the line sync.

The average rise time is 42,5ns (OK) and the average fall time of both falling edges is 23ns (to short).

 

SMPTE 274M-2008 section 10.3 describe the rise and fall times of the line sync as:

10.3 The positive and negative transition of a tri-level sync pulse shall be skew-symmetric with a rise time from 10% to 90% of 4 ±1.5 reference clock periods. The midpoint of each negative transition shall be coincident with its ideal time within a tolerance of ±3 reference clock periods.

 

min: 4-1,5 ref. clock periods => 33,7ns

max: 4+1,5 ref. clock periods => 74,1ns

 

My Register settings are:

0000000 1c10 2003 f04e 0e24 927c 0000 0000 0000

0000010 001b 0000 fa03 1f00 0000 0000 0000 0000

0000020 0000 0000 0000 0000 0000 0000 0000 0000

0000030 7800 0068 4800 a080 8000 0000 0000 0000

0000040 0000 0000 0000 0000 0000 0000 0000 0000

0000050 0000 0000 0000 0000 0000 0000 0000 0000

0000060 0000 0000 0000 0000 0000 0000 0000 0000

0000070 0000 0000 0000 0000 0000 0000 0000 0000

0000080 1000 0b04 0000 0200 0000 0c00 1f7c f021

0000090 0000 0000 0000 0000 0000 0000 0000 0000

00000A0 0000 0000 0000 0000 0000 0000 0000 0000

00000b0 0000 0000 0000 0000 0000 de6a 0042 8119

00000c0 1070 5e12 8026 4a70 8000 0000 0000 0000

00000d0 0000 0000 0000 0000 0000 0000 0000 0000

 

What can I do to configure the ADV7391 to meet the standard requirements?

 

Franz

Outcomes