Why the clock which is coming to the axi_ad9122 in fmcomms1 from the AD board is not regular, I mean the pulse width is not the same everytime. This clock comes as a differential clock to dac_clk_in_p and dac_clk_in_n. These wires are connected with DAC_DCO_P and DAC_DCO_N outputs of ad9523 in the AD board. I check this in the chipscope. Or maybe is the problem with my chipscope. I am clocking the chipscope with 200 MHz, and the adc clock dac_clk_in_p and dac_clk_in_n are supposed to be around 16 MHz. I don't see any mistake here!!!!
Q1: Which clock which is regular (same width pulse everytime) should I feed back from the AD board!?