I have a question regarding AD9834 synchronization. Let me first explain my system and I'll say what I mean by "synchronization".
The system has 10 AD9834 DDS chips on the board. The clock of 72 MHz is common for all DDS chips. The outputs are all 18 MHz, and during the operation the only thing that is changed are the phases. The chips are controlled from one microcontroller, sharing common SDATA and SCLK lines, and corresponding DDS chip is selected/programmed using separate FSYNC line. Also, all chips share common RESET line.
The power-up procedure is as follows:
- upon power-up, put RESET to high
- program all DDS chips (fout = 18 MHz, phase = 0 deg) in sequential order (DDS_1, DDS_2, ..., DDS10).
- put RESET to low
At this moment, all outputs are in phase, i.e. the pahse difference is 0 deg.
During the operation, the microcontroller changes the phase of DDS chips, e.g. phase_1 = 15 deg, then after 3s phase_2 = 15 deg, after another 2s phase_3 = 81 deg, etc.... And everything is working fine.
If I switch on-off several times the clock source, the DDS outputs get different phases, i.e. the phase difference between (in this example) phase_1 and phase_2 is not 0 deg, but it is 90 deg, or 180 deg, or any multiple of 90 deg (because I have 18MHz output with 72MHz clock => 4 samples from look-up table = 90 degrees difference). After this, applying common RESET signal puts the things back in order.
So, by "synchronization" in my case, I don't mean the update of the DDS outputs at the same time (since I'm not using the common FSYNC line). What I need is a system that will ALWAYS start from the "same point" in terms of the phases and the phase differences upon the power-up, or if during the operation something couse problems with clock (that will make the phase desynchronisation - phase differences are changed, but without programming a new phase values) and then to "synchronize" it back again.
I have red the AD9834 datasheet, application notes AN-578 and AN-605, and discussion on the page http://ez.analog.com/thread/4617, and on the new design I'll apply all the rules regarding the common CLOCK and common RESET distribution. So, finally the question. Is it enough just to have common RESET to be sure that the system will always keep the phases as thay should be (without this n x 90 deg phase jumps) - both after the power-up and in-operation RESET ?
Since I'm here, let me ask another question regarding AD9834, although it is related to DDS in general. Let's say that with Fmclk = 72 MHz I need output of Fout = Fmclk / 2 = 36 MHz. Following the power-up procedure described above, the output will give some very small amplitude (almost 0). But if I add phase shift of 90 deg, then the output amplitude is ok (Vpp = 250mV). Now, I think that I understand why is this - theoretical maximum output frequency is Fmclk/2 => two samples from look-up table. If the look-up table is sin() , then these two samples are just the ones around zero amplitude cros section (sin(0)=0 and sin(180)=0). But with the 90 deg phase shift, two samples are the ones at the maximum (sin(90)=1 and sin(270)=-1).
Finally the question:
Does this mean that in the case of DDS, if the desired frequency is Fmclk/2 or very close to that, during the phase sweeping from 0 to 360 deg at one moment the amplitude will fall down to 0 or very close to that? If yes, this can be a problem in certain designs, and what to do to overcome this problem?
Thank you and I apologize if I put too much details.