We are using a 40MHz single ended clock driver chip that produces a 1.8V pk-pk square wave. To get this down to 1.3V we use a resistor divider followed by a series cap (0.1uF) for DC blocking into the AD9361's pin M12 with M11 floating. We are in the process of tuning the resistor divider to get a good square wave of the right amplitude and minimize wasted current in the divider. There is a wide range of compromises in doing this.
My question is what is the recommended rise time of the clock input? If you don't have numbers a verbal description of how it should visually appear on a scope may do the job.