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AD9520-4 EVM clock distribution problem

Question asked by amon on Mar 4, 2015
Latest reply on Mar 20, 2015 by Kyle.Slightom

Good day

 

I am trying to use the AD9520-4 EVM as a clock distribution network (using the CLK connector on the board as input) but I get nothing other than clean 0V DC signals on the outputs (checked on an oscilloscope).

 

  • I have tried the Mode 1 settings in Table 23 of the AD9520_4 datasheet.
  • I have tried bypassing the VCO divider and/or the channel dividers.
  • I have probed the CLK differential pins on the chip (the signal is there).
  • It doesn't look like there are any soldering faults concerning the CLK input.
  • The clock distribution network works perfectly when using the internal VCO as input instead of CLK.
  • The internal PLL works perfectly.

 

Am I missing something or do I have a faulty CLK input on my chip?

 

Thank you

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