Hi every one,
I want to drive LVDS clock for AD9747 from Spartan3E. What I read from AD9747 datasheet was that the minimum LVDS pair is 400mV but from xilinx datasheet I found that typically it is around 350mV. What can I do? Should I just connect the FPGA to CLK inputs with termination like what Analog device suggested in their datasheet? How about common voltage? the common voltage of FPGA is 1.2V but AD9747 needs 400mV. I really confused about this abnormal LVDS receiver.
I really appreciate if some one can help me to understand what should I do.