I have encountered some serious problems in my design with ADCLK925. My design followed the evaluation board of ISLA224P25. But when the board is running, ENOB is only 8bit more of less, and then I found that the clock is very bad as figure 1 shown.
The evaluation board clock module design followed as fig 2.
My board has two ADCs (ISLA224P13) , so I use ADCLK925 instead of ADCLK905 (they are pin-compatible), as shown as fig.3, my design is nearly the same as the evaluation design.
My design is FMC card, The PCB is shown as fig.4. The clk1 and clk2 both were routed with same length 2500mil. All the differential pairs are 100ohm terminated. And single ended line is 50 ohm.
As shown in the figure, I considered the problem maybe the resistence dismatch. But I changed the resistence of R66 and R67 from 100ohm to 250ohm. The clock changed little.
(a) R66,R67 = 249ohm
(C)R66,R67 = 150ohm
During the test, I found the clock level output from ADCLK925 is negtive. But in the ADCLK925 datasheet, the output level is between 1.37V -2.37V.
I found another application of ADCLK925(CN0290_cn.pdf) from www.analog.com website. The design is shown as followed. The R7 use 150ohm for 50 ohm terminated.The 33ohm resistor is used to decrease the output level due to the document.
I have tried all my best to improve the quality of clock output of ADCLK925, Please help me found the problem and fix it.