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Sampling CTRL_OUT bus on AD9361

Question asked by ajo115 on Mar 3, 2015
Latest reply on Mar 4, 2015 by ajo115


We'd like to use the 8-bit CTRL_OUT bus on the AD9361 to read internal state data of the chip during operation (via an FPGA that is hooked up to the 8-bit CTRL_OUT bus).  Is there a clock signal that should be used to qualify when data on the CTRL_OUT bus is valid?  We don't see any mention of any clock signal available for this purpose in the user guide or any of the reference manuals.


Thanks much,