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Handling IRQ AXI DMA Controller

Question asked by MiTfreak on Mar 3, 2015
Latest reply on Mar 5, 2015 by MiTfreak
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Hi all,


I am using No Os reference design for fmcomms1. I wrote functions for handling interrupts

from AXI DMA Controller based on informations that I found here  FPGA Reference Designs: PCORE Register Map [Analog Devices Wiki] . Also I use this document to implement interrupt functions:


Two weeks ago Lars suggested me that I should send data on every SOT IRQ in order to make data

continuously flow from PS to PL. I am able to handle IRQ. But I have difficulties with loading new data.

I want to implement continuous streaming of data from PS to PL, to feed my Tx which is implemented on

PL with data. Interrupt handler is working, so probably I am close to make it work.


Here are questions:


1. What you consider as one transfer in this document FPGA Reference Designs: PCORE Register Map [Analog Devices Wiki]

    Is one transfer just 64 bits (or 32 bits if we configure bus so), or transfer is complete chunk of X_LENGTH bytes (that we specify

    in 0x0418 register) ??? I am confused with this. Because based on what I see from running current code. I see that I get interrupt

    after I send 64 bits. So probably in interrupt handler function I should increase SRC_ADDRESS by 8 on every interrupt, to be able to         send all X_LENGTH bytes?

2. Based on document CURRENT_SRC_ADDRESS is address from which next data sample is read.  What you consider as

    sample? Referring to first question, is sample 64 bits or something else?

If you have a sequence which I should follow, please write me. I know that first thing is to Initialize AXI DMA channel by

setting CONTROL on ENABLE... Then to set SRC adress of data, specify length of data (this one is a little bit confusing,

if I get interrupt on every 64 bits why this is important at all)...


Thank you in advance on answers,


Kind Regards,