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Timing requirements on AD9956 I/O_UPDATE

Question asked by PhilH on Mar 3, 2015
Latest reply on Mar 3, 2015 by DSB

I'm putting the AD9956 into an instrument.   It's going on its own small board in its own box, with an FFC cable connection for control and power, with logic optocouplers to drive the interface.

 

I'm planning to wire I/O_UPDATE to !CS, so that the registers get updated when chip select goes away.  However, as the MCU is asynchronous to the SYNC_CLK signal, and SYNC_CLK is 100 MHz, I'll certainly be violating the 7 ns setup time on I/O_UPDATE. (There's only a 3-ns window out of the 10 ns period.)  In addition, the rise/fall times of the logic opto are 15 ns typical, so I won't be sending it a nice crisp high speed I/O_UPDATE signal.

 

I sort of doubt that this is unusual, but could somebody in the know confirm to me that there won't be any misbehaviour due to not hitting the 3 ns allowed time window for I/O_UPDATE?  That is, it might update a cycle late, which I don't care about, but it won't scribble on any registers or go metastable or anything like that, right?

 

Thanks

 

Phil Hobbs

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