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AD7767 Tsettle specification incorrect?

Question asked by olaf.vandenberg on Mar 3, 2015
Latest reply on Mar 25, 2015 by olaf.vandenberg

Hello everybody,

 

In the AD7767 datasheet (rev C) the value Tsettling in the table on page 5 of 24 is specified as:

(592 × n) + 2 in mclk cycles. (digital filter settling time plus 2 mclk cycles for power-up and reset I assume)

For the AD7767-2, n = 4 so we would have a settling time of 2370 mclk cycles. (2.893 ms)

If I measure the between the rising edge of the mclk after the sync goes high and the last rising edge before the drdy goes down, I measure 2.8767 ms.

If I export my oscilloscope data and analyze it in scilab, I count 2358 mclk periods in this time, so I would say there is a significant difference between what is specified in the datasheet for this time, and what is actually coming out of the hardware.

 

Am I missing something here or interpreting something not correctly or is the specification incorrect?

I need this settling time specification to get a proper phase alignement with other ADCs (different types) in my system.

 

Best regards,

 

Olaf

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