I have an AD9680 evaluation board running with the DAQ2 FPGA reference design on the ZC706. For this evaluation board, I supply an external ADC sample clock and an external FPGA ref_clk and everything is working when the sample clock is 1000 MHz and the FPGA ref_clk is 500 MHz.
I'd like to run the sample clock at 750 MHz and the FPGA ref_clk at 375 MHz, but if I slow the clocks to these rates, the JESD204B RX PLL no longer locks. I don't know exactly where the cutoff is, but 900 MHz and 450 MHz works while 800 MHz and 400 MHz does not.
From my efforts to get this AD9680 evaluation board working with the DAQ2 FPGA reference design, I know that the Linux driver / devicetree / FPGA design / JESD204B setup is a delicate ecosystem that is easily disturbed, but after spending a couple of days going through documentation and experimenting, I have not yet solved how to run it with the sample clock at 750 MHz instead of 1000 MHz. I'm hoping that I do not need to rebuild the FPGA with a different configuration of the JESD204B block. The serial link data rate should be going from 10.0 Gbps to 7.5 Gpbs, which I think means that the two rates can be run in the same mode since they are both between 6.25 Gbps and 12.5 Gbps.
Is there anyone who knows all of the files that need to change in order to make this work?
Thanks in advance,