Hi,

I need to how many PCLK cycles are needed to process interpolation step in FIR Accelerator of ADSP21489? For example, if input sample buffer contains 4 samples which need to produce 32 samples after interpolation process with interpolation factor is 8 so in this case M=8, W=32 and N=100, how many cycles will it be needed? Any theoratical formula is available like given for decimation in Sharc hardware manual?

Best Regards,

Mussab

Hi Mussab,

Unfortunately, looks like we don't have such expression already available for the interpolation case. However, I believe, the number of cycles for the interpolation case should ideally be almost equal to or less than the number of cycles required to process W samples without interpolation. The reason being that the FIR is still processing for W output samples even if it is using only W/M input samples for the same. Thus, if you are looking for worst case numbers, you can still calculate the same using the throughput expression without interpolation.

I measured the numbers on ADSP-21469 sometime back for window size = 512 and taps = 1024 and got the following numbers.

In case you are interested in actual numbers, you can modify the attached code for ADSP-21489 and measure the numbers your self for a particular combination of W and N.

Hope this helps. Please do let me know if you still have doubts.

Thanks,

Mitesh