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ADV7391 - Video out problem

Question asked by Satheesh-R on Mar 2, 2015
Latest reply on Mar 2, 2015 by Satheesh-R

Hi,

 

We have a customized bf609 board,interfaced with encoder ADV7391. currently i am facing problem with the output of encoder.

There is a color pattern present in every start of line on the video frame image.When HSYNC is monitored, there is spike at the every end of sync signal. The monitored DSO image wtih the output video image is attached for your referral.

 

Below given the Encoder,PPI configurations

 

void encoder_init(void)

{

  unsigned int nSubCrDiv = 0;

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x17, 0x02, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x00, 0x11, 2,false); //DAC 1 ON, SLEEP Mode

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x01, 0x00, 2,false); // YPbPr

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x02, 0x20, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x0D, 0x00, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x82, 0xCB, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x83, 0x04, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x84, 0x00, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x86, 0x08, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x87, 0x08, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x80, 0xF1, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x8A, 0x2C, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x8B, 0x80, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x89, 0x28, 2,false);//0x20

 

  nSubCrDiv = 0x2A098ACB;//0x2A2D9933;//;

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x8C, nSubCrDiv, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x8D, nSubCrDiv >> 8, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x8E, nSubCrDiv >> 16, 2,false);

  twi_WriteReg(TWI_MASTER,TWI_ENC_ADDR, 0x8F, nSubCrDiv >> 24, 2,false);

}


void InitEPPI2(void)

{

       InitEPPI2DMA();

 

       *pREG_EPPI2_CTL = ENUM_EPPI_CTL_INTERLACED |

                                            ENUM_EPPI_CTL_FLDSEL_HI |

                                            ENUM_EPPI_CTL_SYNC2 |

                                            ENUM_EPPI_CTL_INTFS |

                                            ENUM_EPPI_CTL_BLANKGEN |

                                            ENUM_EPPI_CTL_POLC10 |

                                            ENUM_EPPI_CTL_ACTIVE656 |

                                            ENUM_EPPI_CTL_FS1LO_FS2LO |

                                            ENUM_EPPI_CTL_TXMODE |

                                            ENUM_EPPI_CTL_PACK_EN|

                                            ENUM_EPPI_CTL_DLEN08;

  ssync();

 

  /**pREG_EPPI2_FS1_DLY = 286;

  ssync();*/

 

  *pREG_EPPI2_LINE  = 1726;

   ssync();

  *pREG_EPPI2_FRAME = 625;

  ssync();

  *pREG_EPPI2_HCNT  = 1440;

  ssync();

  *pREG_EPPI2_VCNT  = 576;

  ssync();

/**pREG_EPPI2_HDLY = 10000;

  ssync();*/

  *pREG_EPPI2_FS1_WLHB = 286;//288 sync width 1728 - 1440;

  ssync();

*pREG_EPPI2_FS1_PASPL = 1440;//Period

  ssync();

 

  *pREG_EPPI2_FS2_WLVB = ((01  << BITP_EPPI_FS2_WLVB_F2VBAD) | \

                                                     (24  << BITP_EPPI_FS2_WLVB_F2VBBD) | \

                                                     (01  << BITP_EPPI_FS2_WLVB_F1VBAD) | \

                                                     (23  << BITP_EPPI_FS2_WLVB_F1VBBD));

  ssync();

 

 

  *pREG_EPPI2_FS2_PALPF = ((288 << BITP_EPPI_FS2_PALPF_F2ACT) | (288 << BITP_EPPI_FS2_PALPF_F1ACT));

  ssync();

}

 

 

 

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