I am using the AD9910 evaluation board in order to use the parallel data port to modulate phase and frequency. I have an issue with the pdclk signal. I see an extremely weak signal on the pdclk pin (J8). I am not using the evaluation board software but a FPGA so my jumper settings are set accordingly. I do notice the syncclk signal and using the SPI command I can shut down the syncclk (which means my SPI communication is working). When the reference clock is set to 1GHz, the output at the pdclk pin is extremely low and it reaches max amplitude when the ref clock is set to around 700MHz (at this ref freq, the output is around 120mVpp). I ran the eval board software again to check if the board is working, and it is. Here too, the pdclk pin does show a very weak signal (around 38mVpp) when the DDS board is run using the eval board. Why is this signal so weak? I saw this thread for the AD9957: https://ez.analog.com/message/59556#59556 but KennyG says the PDCLK is buffered on the eval board. So I am assuming it is buffered on the AD9910 board as well. Do I need to change something on the board to increase the amplitude? Any help would be great. Thanks!