I am using ADSP21489 Ez-board to convert audio analog signal to I2S digital signal, the three lines of I2S signal: data, lrclk, and bclk, as well as the mclk are then fed to another audio power amplifier board as the input.
The example code "AnalogInDigitalOut" is used as the template, in this project the analog input signal is converted to spdif signal, SPORT2 transmits the digital signal in I2S mode, and TDM mode is used to generate the master clock, which is routed to DAI_PB07.
My question is:
The bit clock for spdif and i2s in this project is generated by the PCG, and the lrclk (frame sync) is generated by the ADC, which is routed to DAI_PB08. I measured these two clocks on the oscilloscope and noticed that the falling edge of the bclk was not aligned to the transition edges of lrclk, which is required by I2S format, as shown in the following picture.
I connect these two clocks to the audio amplifier digital input, and no sound is output. I tried to generate both the bclk and lrclk by PCG and alignment is OK, but the I2S data are not coincide with the lrclk.
So for spdif transmission, is it unnecessary to align the bclk and lrclk?
If I want to align these two clocks to meet the requirement of I2S standard, is there any other way I can try to implement the conversion between analog to I2S?