The AD6676 datasheet, Table 2 states that SYNCINB differential input can bear maximum 1.8V.
On the AD6676EVB schematic sheet 7, it says DSYNCB DIFF -> 2.5V LVDS.
Looking at the vc707+ad6676evb refdes .xdc file the ports rx_sync_p and rx_sync_n which are connected to SYNCINB of the AD6676 are driven by IOSTANDARD LVDS
In xc706+ad6676evb refdes .xdc file same ports are driven by LVDS_25 standard.
Can you please comment on this.
And I have an FPGA carrier in which SYNCINB inputs of AD6676 is corresponds to HR pins which can only work with LVDS25 like the XC706 board. So to my understanding it should not be a problem to use AD6676 eval board with my FPGA carrier? Am I right?