AnsweredAssumed Answered

AD9361 Gain Mode Data Port Timing Issues

Question asked by andrew.dickson on Feb 27, 2015
Latest reply on Mar 9, 2015 by rgetz



We have been testing the various different gain modes of the AD9361 chip using our test FPGA platform on the FMCOMMS3/Zedboard and no-OS reference design.


Using Vivado debugger, we can monitor the samples out of the AD9361 IP core interface and also directly monitor the RX[5:0] and RX-FRAME signals at the Input buffer. We are running the chip in 1R1T mode, FDD, LVDS.


For some reason we are seeing a strange timing issue with the samples in an AGC (Fast or Slow) modes. In this mode we are seeing the start or the sample being the LSB's when RX_FRAME_P is low. This doesn't happen everytime we start the processor, but is roughly 50% of the time. We have tried and repeated this on more that 1 Zedboard/FMCOMMS3 system. Once we demultiplex the databus in the FPGA, there is a mis-alignment between the 6 MSB's and  6 LSB's of the full 12-bit sample. This is the same for both I & Q. 


We are aware that normally the MSB are sent first and the RX_FRAME_P is high. PLEASE BE AWARE, THIS DOES NOT OCCUR IN MGC MODE. In fact, using breakpoints, we can set the device into Slow or Fast AGC mode and see the problem. The we continue to next breakpoint to switch into MGC mode which actually corrects the misalignment. This proves this is a setting/mode issue in the chip and not in the FPGA. Also, we can eradicate the issue by running the code like this: Initialize in Slow/Fast Attack mode --> change to MGC mode --> add a delay (e.g write new gain setting) --> set back to Slow/Fast Attack mode. This seems to be a reliable woraround

Note: This doesn't always work unless you have the delay, i.e. it has to be in MGC mode for some time element to make this workaround more reliable.


Please could you help with this confusing issue.  I have attached the Vivado debugger screenshots to help understand this. (Note: signal at top of page are not labelled correctly but they represent the RX[5:0] and FRAME signals (...693..= bit 5, etc.)


If you wish to discuss this offline then please do, I believe this is a definite issue with the chip, unless it is a known issue with a different workaround? Perhaps some extra calibration required? I just don't understand the link between the AGC modes and the Data port!