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AD9361 parameters

Question asked by TothR on Feb 27, 2015
Latest reply on Mar 10, 2015 by mhennerich

Hi,

 

I have a question in connection of the AD9361 chip. I have found sourcefiles on analogdevice github, and I would like to get more information about the parameters in the AD9361: sw/main.c Source File

 

Could you please send me a link, where can I find more information about what and how  these parameters affect?

There is a 6 element array among the parameters:

{983040000, 245760000, 122880000, 61440000, 30720000, 30720000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

Which clock drives what?

 

The parameters:

 

  82 AD9361_InitParam default_init_param = {

  83   /* Identification number */

  84  0,  //id_no;

  85   /* Reference Clock */

  86  40000000UL,  //reference_clk_rate

  87   /* Base Configuration */

  88  1,  //two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable

  89  1,  //frequency_division_duplex_mode_enable *** adi,frequency-division-duplex-mode-enable

  90  0,  //tdd_use_dual_synth_mode_enable *** adi,tdd-use-dual-synth-mode-enable

  91  0,  //tdd_skip_vco_cal_enable *** adi,tdd-skip-vco-cal-enable

  92  0,  //tx_fastlock_delay_ns *** adi,tx-fastlock-delay-ns

  93  0,  //rx_fastlock_delay_ns *** adi,rx-fastlock-delay-ns

  94  0,  //rx_fastlock_pincontrol_enable *** adi,rx-fastlock-pincontrol-enable

  95  0,  //tx_fastlock_pincontrol_enable *** adi,tx-fastlock-pincontrol-enable

  96  0,  //external_rx_lo_enable *** adi,external-rx-lo-enable

  97  0,  //external_tx_lo_enable *** adi,external-tx-lo-enable

  98  5,  //dc_offset_tracking_update_event_mask *** adi,dc-offset-tracking-update-event-mask

  99  6,  //dc_offset_attenuation_high_range *** adi,dc-offset-tracking-update-event-mask

  100  5,  //dc_offset_attenuation_low_range *** adi,dc-offset-tracking-update-event-mask

  101  0x28,  //dc_offset_count_high_range *** adi,dc-offset-tracking-update-event-mask

  102  0x32,  //dc_offset_count_low_range *** adi,dc-offset-tracking-update-event-mask

  103  0,  //tdd_use_fdd_vco_tables_enable *** adi,tdd-use-fdd-vco-tables-enable

  104  0,  //split_gain_table_mode_enable *** adi,split-gain-table-mode-enable

  105  MAX_SYNTH_FREF, //trx_synthesizer_target_fref_overwrite_hz *** adi,trx-synthesizer-target-fref-overwrite-hz

  106  0,  // qec_tracking_slow_mode_enable *** adi,qec-tracking-slow-mode-enable

  107   /* ENSM Control */

  108  0,  //ensm_enable_pin_pulse_mode_enable *** adi,ensm-enable-pin-pulse-mode-enable

  109  0,  //ensm_enable_txnrx_control_enable *** adi,ensm-enable-txnrx-control-enable

  110   /* LO Control */

  111  2400000000UL,  //rx_synthesizer_frequency_hz *** adi,rx-synthesizer-frequency-hz

  112  2400000000UL,  //tx_synthesizer_frequency_hz *** adi,tx-synthesizer-frequency-hz

  113   /* Rate & BW Control */

  114  {983040000, 245760000, 122880000, 61440000, 30720000, 30720000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

  115  {983040000, 122880000, 122880000, 61440000, 30720000, 30720000},//uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

  116  18000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz

  117  18000000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz

  118   /* RF Port Control */

  119  0,  //rx_rf_port_input_select *** adi,rx-rf-port-input-select

  120  0,  //tx_rf_port_input_select *** adi,tx-rf-port-input-select

  121   /* TX Attenuation Control */

  122  10000,  //tx_attenuation_mdB *** adi,tx-attenuation-mdB

  123  0,  //update_tx_gain_in_alert_enable *** adi,update-tx-gain-in-alert-enable

  124   /* Reference Clock Control */

  125  0,  //xo_disable_use_ext_refclk_enable *** adi,xo-disable-use-ext-refclk-enable

  126  {8, 5920},  //dcxo_coarse_and_fine_tune[2] *** adi,dcxo-coarse-and-fine-tune

  127  0,  //clk_output_mode_select *** adi,clk-output-mode-select

  128   /* Gain Control */

  129  2,  //gc_rx1_mode *** adi,gc-rx1-mode

  130  2,  //gc_rx2_mode *** adi,gc-rx2-mode

  131  58,  //gc_adc_large_overload_thresh *** adi,gc-adc-large-overload-thresh

  132  4,  //gc_adc_ovr_sample_size *** adi,gc-adc-ovr-sample-size

  133  47,  //gc_adc_small_overload_thresh *** adi,gc-adc-small-overload-thresh

  134  8192,  //gc_dec_pow_measurement_duration *** adi,gc-dec-pow-measurement-duration

  135  0,  //gc_dig_gain_enable *** adi,gc-dig-gain-enable

  136  800,  //gc_lmt_overload_high_thresh *** adi,gc-lmt-overload-high-thresh

  137  704,  //gc_lmt_overload_low_thresh *** adi,gc-lmt-overload-low-thresh

  138  24,  //gc_low_power_thresh *** adi,gc-low-power-thresh

  139  15,  //gc_max_dig_gain *** adi,gc-max-dig-gain

  140   /* Gain MGC Control */

  141  2,  //mgc_dec_gain_step *** adi,mgc-dec-gain-step

  142  2,  //mgc_inc_gain_step *** adi,mgc-inc-gain-step

  143  0,  //mgc_rx1_ctrl_inp_enable *** adi,mgc-rx1-ctrl-inp-enable

  144  0,  //mgc_rx2_ctrl_inp_enable *** adi,mgc-rx2-ctrl-inp-enable

  145  0,  //mgc_split_table_ctrl_inp_gain_mode *** adi,mgc-split-table-ctrl-inp-gain-mode

  146   /* Gain AGC Control */

  147  10,  //agc_adc_large_overload_exceed_counter *** adi,agc-adc-large-overload-exceed-counter

  148  2,  //agc_adc_large_overload_inc_steps *** adi,agc-adc-large-overload-inc-steps

  149  0,  //agc_adc_lmt_small_overload_prevent_gain_inc_enable *** adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable

  150  10,  //agc_adc_small_overload_exceed_counter *** adi,agc-adc-small-overload-exceed-counter

  151  4,  //agc_dig_gain_step_size *** adi,agc-dig-gain-step-size

  152  3,  //agc_dig_saturation_exceed_counter *** adi,agc-dig-saturation-exceed-counter

  153  1000,  // agc_gain_update_interval_us *** adi,agc-gain-update-interval-us

  154  0,  //agc_immed_gain_change_if_large_adc_overload_enable *** adi,agc-immed-gain-change-if-large-adc-overload-enable

  155  0,  //agc_immed_gain_change_if_large_lmt_overload_enable *** adi,agc-immed-gain-change-if-large-lmt-overload-enable

  156  10,  //agc_inner_thresh_high *** adi,agc-inner-thresh-high

  157  1,  //agc_inner_thresh_high_dec_steps *** adi,agc-inner-thresh-high-dec-steps

  158  12,  //agc_inner_thresh_low *** adi,agc-inner-thresh-low

  159  1,  //agc_inner_thresh_low_inc_steps *** adi,agc-inner-thresh-low-inc-steps

  160  10,  //agc_lmt_overload_large_exceed_counter *** adi,agc-lmt-overload-large-exceed-counter

  161  2,  //agc_lmt_overload_large_inc_steps *** adi,agc-lmt-overload-large-inc-steps

  162  10,  //agc_lmt_overload_small_exceed_counter *** adi,agc-lmt-overload-small-exceed-counter

  163  5,  //agc_outer_thresh_high *** adi,agc-outer-thresh-high

  164  2,  //agc_outer_thresh_high_dec_steps *** adi,agc-outer-thresh-high-dec-steps

  165  18,  //agc_outer_thresh_low *** adi,agc-outer-thresh-low

  166  2,  //agc_outer_thresh_low_inc_steps *** adi,agc-outer-thresh-low-inc-steps

  167  1,  //agc_attack_delay_extra_margin_us; *** adi,agc-attack-delay-extra-margin-us

  168  0,  //agc_sync_for_gain_counter_enable *** adi,agc-sync-for-gain-counter-enable

  169   /* Fast AGC */

  170  64,  //fagc_dec_pow_measuremnt_duration *** adi,fagc-dec-pow-measurement-duration

  171  260,  //fagc_state_wait_time_ns *** adi,fagc-state-wait-time-ns

  172   /* Fast AGC - Low Power */

  173  0,  //fagc_allow_agc_gain_increase *** adi,fagc-allow-agc-gain-increase-enable

  174  5,  //fagc_lp_thresh_increment_time *** adi,fagc-lp-thresh-increment-time

  175  1,  //fagc_lp_thresh_increment_steps *** adi,fagc-lp-thresh-increment-steps

  176   /* Fast AGC - Lock Level */

  177  10,  //fagc_lock_level *** adi,fagc-lock-level */

  178  1,  //fagc_lock_level_lmt_gain_increase_en *** adi,fagc-lock-level-lmt-gain-increase-enable

  179  5,  //fagc_lock_level_gain_increase_upper_limit *** adi,fagc-lock-level-gain-increase-upper-limit

  180   /* Fast AGC - Peak Detectors and Final Settling */

  181  1,  //fagc_lpf_final_settling_steps *** adi,fagc-lpf-final-settling-steps

  182  1,  //fagc_lmt_final_settling_steps *** adi,fagc-lmt-final-settling-steps

  183  3,  //fagc_final_overrange_count *** adi,fagc-final-overrange-count

  184   /* Fast AGC - Final Power Test */

  185  0,  //fagc_gain_increase_after_gain_lock_en *** adi,fagc-gain-increase-after-gain-lock-enable

  186   /* Fast AGC - Unlocking the Gain */

  187   /* 0 = MAX Gain, 1 = Optimized Gain, 2 = Set Gain */

  188  0,  //fagc_gain_index_type_after_exit_rx_mode *** adi,fagc-gain-index-type-after-exit-rx-mode

  189  1,  //fagc_use_last_lock_level_for_set_gain_en *** adi,fagc-use-last-lock-level-for-set-gain-enable

  190  1,  //fagc_rst_gla_stronger_sig_thresh_exceeded_en *** adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable

  191  5,  //fagc_optimized_gain_offset *** adi,fagc-optimized-gain-offset

  192  10,  //fagc_rst_gla_stronger_sig_thresh_above_ll *** adi,fagc-rst-gla-stronger-sig-thresh-above-ll

  193  1,  //fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en *** adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable

  194  1,  //fagc_rst_gla_engergy_lost_goto_optim_gain_en *** adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable

  195  10,  //fagc_rst_gla_engergy_lost_sig_thresh_below_ll *** adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll

  196  8,  //fagc_energy_lost_stronger_sig_gain_lock_exit_cnt *** adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt

  197  1,  //fagc_rst_gla_large_adc_overload_en *** adi,fagc-rst-gla-large-adc-overload-enable

  198  1,  //fagc_rst_gla_large_lmt_overload_en *** adi,fagc-rst-gla-large-lmt-overload-enable

  199  0,  //fagc_rst_gla_en_agc_pulled_high_en *** adi,fagc-rst-gla-en-agc-pulled-high-enable

  200  0,  //fagc_rst_gla_if_en_agc_pulled_high_mode *** adi,fagc-rst-gla-if-en-agc-pulled-high-mode

  201  64,  //fagc_power_measurement_duration_in_state5 *** adi,fagc-power-measurement-duration-in-state5

  202   /* RSSI Control */

  203  1,  //rssi_delay *** adi,rssi-delay

  204  1000,  //rssi_duration *** adi,rssi-duration

  205  3,  //rssi_restart_mode *** adi,rssi-restart-mode

  206  0,  //rssi_unit_is_rx_samples_enable *** adi,rssi-unit-is-rx-samples-enable

  207  1,  //rssi_wait *** adi,rssi-wait

  208   /* Aux ADC Control */

  209  256,  //aux_adc_decimation *** adi,aux-adc-decimation

  210  40000000UL,  //aux_adc_rate *** adi,aux-adc-rate

  211   /* AuxDAC Control */

  212  1,  //aux_dac_manual_mode_enable *** adi,aux-dac-manual-mode-enable

  213  0,  //aux_dac1_default_value_mV *** adi,aux-dac1-default-value-mV

  214  0,  //aux_dac1_active_in_rx_enable *** adi,aux-dac1-active-in-rx-enable

  215  0,  //aux_dac1_active_in_tx_enable *** adi,aux-dac1-active-in-tx-enable

  216  0,  //aux_dac1_active_in_alert_enable *** adi,aux-dac1-active-in-alert-enable

  217  0,  //aux_dac1_rx_delay_us *** adi,aux-dac1-rx-delay-us

  218  0,  //aux_dac1_tx_delay_us *** adi,aux-dac1-tx-delay-us

  219  0,  //aux_dac2_default_value_mV *** adi,aux-dac2-default-value-mV

  220  0,  //aux_dac2_active_in_rx_enable *** adi,aux-dac2-active-in-rx-enable

  221  0,  //aux_dac2_active_in_tx_enable *** adi,aux-dac2-active-in-tx-enable

  222  0,  //aux_dac2_active_in_alert_enable *** adi,aux-dac2-active-in-alert-enable

  223  0,  //aux_dac2_rx_delay_us *** adi,aux-dac2-rx-delay-us

  224  0,  //aux_dac2_tx_delay_us *** adi,aux-dac2-tx-delay-us

  225   /* Temperature Sensor Control */

  226  256,  //temp_sense_decimation *** adi,temp-sense-decimation

  227  1000,  //temp_sense_measurement_interval_ms *** adi,temp-sense-measurement-interval-ms

  228  0xCE,  //temp_sense_offset_signed *** adi,temp-sense-offset-signed

  229  1,  //temp_sense_periodic_measurement_enable *** adi,temp-sense-periodic-measurement-enable

  230   /* Control Out Setup */

  231  0xFF,  //ctrl_outs_enable_mask *** adi,ctrl-outs-enable-mask

  232  0,  //ctrl_outs_index *** adi,ctrl-outs-index

  233   /* External LNA Control */

  234  0,  //elna_settling_delay_ns *** adi,elna-settling-delay-ns

  235  0,  //elna_gain_mdB *** adi,elna-gain-mdB

  236  0,  //elna_bypass_loss_mdB *** adi,elna-bypass-loss-mdB

  237  0,  //elna_rx1_gpo0_control_enable *** adi,elna-rx1-gpo0-control-enable

  238  0,  //elna_rx2_gpo1_control_enable *** adi,elna-rx2-gpo1-control-enable

  239   /* Digital Interface Control */

  240  1,  //pp_tx_swap_enable *** adi,pp-tx-swap-enable

  241  1,  //pp_rx_swap_enable *** adi,pp-rx-swap-enable

  242  0,  //tx_channel_swap_enable *** adi,tx-channel-swap-enable

  243  0,  //rx_channel_swap_enable *** adi,rx-channel-swap-enable

  244  1,  //rx_frame_pulse_mode_enable *** adi,rx-frame-pulse-mode-enable

  245  0,  //two_t_two_r_timing_enable *** adi,2t2r-timing-enable

  246  0,  //invert_data_bus_enable *** adi,invert-data-bus-enable

  247  0,  //invert_data_clk_enable *** adi,invert-data-clk-enable

  248  0,  //fdd_alt_word_order_enable *** adi,fdd-alt-word-order-enable

  249  0,  //invert_rx_frame_enable *** adi,invert-rx-frame-enable

  250  0,  //fdd_rx_rate_2tx_enable *** adi,fdd-rx-rate-2tx-enable

  251  0,  //swap_ports_enable *** adi,swap-ports-enable

  252  0,  //single_data_rate_enable *** adi,single-data-rate-enable

  253  1,  //lvds_mode_enable *** adi,lvds-mode-enable

  254  0,  //half_duplex_mode_enable *** adi,half-duplex-mode-enable

  255  0,  //single_port_mode_enable *** adi,single-port-mode-enable

  256  0,  //full_port_enable *** adi,full-port-enable

  257  0,  //full_duplex_swap_bits_enable *** adi,full-duplex-swap-bits-enable

  258  0,  //delay_rx_data *** adi,delay-rx-data

  259  0,  //rx_data_clock_delay *** adi,rx-data-clock-delay

  260  4,  //rx_data_delay *** adi,rx-data-delay

  261  7,  //tx_fb_clock_delay *** adi,tx-fb-clock-delay

  262  0,  //tx_data_delay *** adi,tx-data-delay

  263  150,  //lvds_bias_mV *** adi,lvds-bias-mV

  264  1,  //lvds_rx_onchip_termination_enable *** adi,lvds-rx-onchip-termination-enable

  265  0,  //rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable

  266   /* Tx Monitor Control */

  267  37000,  //low_high_gain_threshold_mdB *** adi,txmon-low-high-thresh

  268  0,  //low_gain_dB *** adi,txmon-low-gain

  269  24,  //high_gain_dB *** adi,txmon-high-gain

  270  0,  //tx_mon_track_en *** adi,txmon-dc-tracking-enable

  271  0,  //one_shot_mode_en *** adi,txmon-one-shot-mode-enable

  272  511,  //tx_mon_delay *** adi,txmon-delay

  273  8192,  //tx_mon_duration *** adi,txmon-duration

  274  2,  //tx1_mon_front_end_gain *** adi,txmon-1-front-end-gain

  275  2,  //tx2_mon_front_end_gain *** adi,txmon-2-front-end-gain

  276  48,  //tx1_mon_lo_cm *** adi,txmon-1-lo-cm

  277  48,  //tx2_mon_lo_cm *** adi,txmon-2-lo-cm

  278   /* GPIO definitions */

  279  -1,  //gpio_resetb; /* reset-gpios */

  280   /* MCS Sync */

  281  -1,  //gpio_sync; /* sync-gpios */

  282  -1,  //gpio_cal_sw1; /* cal-sw1-gpios */

  283  -1  //gpio_cal_sw2; /* cal-sw2-gpios */

  284 };

 

Kind Regards,

Richard

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