I have some questions about AD9915 and parallel port, so here we go:
1. Syncronizing to SYNC_CLOCK timing
So if i sync my parallel port to SYNC_CLOCK i need 2 cycles for writing, because i need to toggle WR pin. Is this correct?
2. How to handle no SYNC_CLOCK at device startup?
Since there will be no SYNC_CLOCK when PPL is disabled i have some problems. I am using this clock to run FSM in FPGA...so it wont be running at all at startup, is there some good advice about this? What write timing should i use when PLL is disabled, i guess i have to send data really slow?
3. Async parallel port
If i decide to not sync parallel port i have to ensure that WR signal(and all othes) is 2x SYNC_CLOCK wide yes?
Will there be some issues with async port, could it happen that write command fails for example? I understand there could be metastability issues, but those happen so rarely it is safe to ignore them?