I´m working with the reference design FMCADC2 in a vc707. The base proyect works fine, but I want to add more spi devices to the SPI bus, and is here where the problems starts.
I have modified the ip core increasing the number of slaves in the bus up to 4, added the location of the pins in the .xdc file and generate the new bitstream. Up to this point no erros or warnings, everything fine. But when I write the software to test the communication something weird happens:
At this point we have 4 SS (Slave Select), 1 SDIO, 1 CLK.
The CS signal of the slave 0 and 1 works fine, they stay in a high state until I select Slave0 or Slave1. But Slave2 and Slave3 are always in low level until I want to read/write to any of the slaves, in that moment, SS2 and SS3 go up and stay there until I finish the reading. In that moment, both signals go down again.
The writing sequence in the imagen below is SS0, SS1, SS2, SS3. As you can see at the begining we have SS0 and SS1 in a high level, but SS2 and SS3 tied down (SS is an active low signal, they should be in a high level too!).
When I start writting to SS0 (SS0 go down), SS1 stays high and SS2 and SS3 go high also!! but as soon as I finish the writting (SS0 go high), SS2 and SS3 go down again .
The second writting is in SS1, and the behavior is the same. SS1 go down, SS2 and SS3 go high but after the reading, SS2 and SS3 go down.
The funny part is when I try to write in Slave3, to select that slave I have to tie down the signal SS3, but that signal is already in a low state, so there is no change, but as always... SS4 goes up during the TX.
Writing to Slave 4 is the same as writting to Slave3.
Any ideas how to solve this problem? If you want any kind of information don´t hesitate and ask for it.