Is there a timing number for the relative delay between the data bus output bits and the framing signal on the Rx side? I am using the device in LVDS mode. The datasheet specifies tDDRX and tDDDV as a minimum of 0.25ns and a max of 1.25ns. Does this mean that the delay between the bits on a given chip in the data bus output can be anywhere between 0.25 and 1.25ns? If so, for a clock period of 4.069ns my data valid window would be 1.0345ns. Is this correct analysis? It seems like 1.0ns difference between the bits of the databus (and the frame) is quite large for a given chip. If this is not correct, then can anyone let me know the correct value for the relative delay between the bits of the databus/framing signal? Thanks!