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AD5932 internal regulator

Question asked by blueskull on Feb 22, 2015
Latest reply on Feb 22, 2015 by LouijieC

Hi, I am designing a DDS based design with LVDS input. I want to use my FPGA's IO (A3P250) to receive LVDS signal. It draws only no more than 2 mA in worst case. Can I use the internal LDO from AD5932?

 

In my scenario, I will not draw any current from MSBOUT, and the MCLK will be 48 MHz.

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