We will connect an external clock source to the reference clock input of AD9364 and as it is of high importance for our side to obtain the best performance we need a better understanding of the chip. We have 5 questions regarding the external reference clock requirements as below:
1) Is the phase noise performance effected by scaling of the external signal? In other words, does applying a 50 MHz signal directly without scaling or applying a 100 MHz signal and scaling it by 1/2 make a difference in terms of phase noise assuming both clock sources have exactly the same phase noise?
2) In the user guide it says the recommended range for RF PLLs for the optimum phase noise is 40 MHz-80 MHz and being the closer to 80 MHz is better. Do you have any figure/plot which gives more insight to phase noise behaviour of this range?
3) Again in the user guide it says the level for the signal should be 1.3V peak to peak maximum and lower swings will limit the performance. Could you elaborate more on the effect of the level to the performance? We would like to know better how much margin we have if we go lower than 1.3V peak to peak.
4) Do you have any figures/plots about the effect of the slew rate of the input signal on the performance since we need to know what would happen even if we would supply the chip with pure sinusoidal signal instead of a clipped sinewave or CMOS signal as suggested in the user guide. As we experience from the demo board it also works with the sine wave.
5) Do you have a figure for the external clock phase noise with respect to the different fundamental frequencies in the 10MHz-80MHz range? In AD9361 reference clock requirements document, the figure given is measured at 40 MHz fundamental frequency. We would like to know how the offset frequency changes for the fundamental frequencies of 50MHz and 80MHz