In our application the DA-converter AD5449 is interfaced with the SPI controller of the i.MX31 processor.
At initialization, the DAC is set up to: full SDO driver, standalone mode, CLR to zero scale, falling active clock edge.
At serial data transfer we set the control bits to 0x3 and 0x6 for load input register (asynchronous update).
The LDAC pin is externally set by a fpga and is normally high.
I measured the serial line and found the serial stream as expected. The timing of SCLK and SYNC works as expected. The timing characteristics is as demanded in the datasheet.
In this configuration the DAC output should be updated when LDAC goes low.
But in our case the DAC is updated on the 16th clock falling edgde.
( Or it is updated when SYNC goes high; it can not be measured exactly because the update rate of the output signal is relatively slow.)
But it is definitely not, when LDAC goes low.
Our LDAC signal comes with a repetition rate of 1kHz and has no time relation to the serial data transfer to the DAC.
So it happens most of the time, that the LDAC goes low without the input shift registers of the DAC were updated. I assume this brings the DAC to a synchronous update mode.
Can you confirm that?
A second question is, what happens, when LDAC toggles in between a serial transfer?
Anyone who can help?