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Custom IP and problems with registers in software part.

Question asked by Jetmiri on Feb 18, 2015
Latest reply on Feb 18, 2015 by CsomI

Hi everyone,

 

I am using FMCOMMS1 with Zedboard. I am trying to place a zigbee transmitter IP between axi_ad9122 and axi_dma. So it will take data from the DMA and it will produce I and Q data for axi_ad9122. I checked the probes but at the output of the zigbee transmitter IP i didn't have anything. To test I used just constant values at the input of zigbee transmitter IP even though the clock that I inserted at the zigbee transmitter IP was working correctly. After searching at the forum posts I saw that it is not a good idea to ad new IPs at reference design since it will change the registers space for the software part. So for the second test I incorporated the zigbee IP inside the axi_ad9122 IP. Again I used constant inputs but again without success at the output of I and Q parts from the zigbee transmitter IP. My code is working perfectly in simulation in QuestaSim.

 

Q1. Is there any problem to take constants at input of the IP in verilog!? It is supposed to take the value every time the clocks comes, am I right or not!?

 

Q2: If I use a custom IP between DMA and axi_ad9122 should I change anything in software part, or the right connection of IP in the Vivado Design is enough for the flow of data!?


Regards,

Jetmir

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