This question is related to my previous question Interfacing PS and PL (streaming data from PS to PL) . I have implemented FIFO buffer on PS side (buffer is mapped to shared memory between PS and axi_ad9122_dma), so now I am able to send data to DAC continuously (basically I have buffer with packets from MAC Layer, and I cyclic send them to DAC). Now, I want to put my Tx IP (I already implemented this in System Verilog, and in simulation it is working), between ax_ad9122_dma and axi_ad9122 to make PHY layer framing and modulation. But again I need some sort of advice (or how to).
I implemented functions for handling interrupts from ad9122 on PS. So I am able to directly stream data from PS to DAC, without Tx in between. What I do not understand, if I put my Tx IP, which has this inputs:
clk (clock signal at the input),
rst (reset signal),
start (start signal, indicating when there is data from MAC layer to send),
length (length of packet) [6:0],
data (raw MAC layer packet) [7:0],
modclk (clock at output),
modIout (I branch output) [7:0],
modQout (Q branch output) [7:0])
how I will be able to control DAC and to handle interrupts from DAC (I need to wait Tx to process data before I can send another packet of data)? Is there any example in which there is custom IP block between axi_dma_9122 and axi_ad9122 which is doing some procession of data?
Thank you in advance on answer,