I was trying to build reference design with:
using hdl sources:
on Vivado 2014.2 WebPack.
When I compiled all used libraries and start hdl/project/fmcomms1/zed/system_project.tcl to build project this issue was occur:
[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified.
Please check your design and connect them if needed:
How should I fix it?