AnsweredAssumed Answered

FMCOMMS1 - ZedBoard seting up DMA channel

Question asked by DesiJ on Feb 15, 2015
Latest reply on Feb 19, 2015 by DragosB

Hi,

 

I am trying to set up streaming of packets (127 bytes of data) from PS to PL, by using NO-OS reference design. As first step I implemented FIFO buffer on PS to store packets on memory allocated for DAC DMA. This part (for writing in memory) is working correctly. Now I am trying to make functions : gor initialization of AXI DMA, for starting DMA transfer, for Interrupt handling ... I explored test.c from reference design ( and Register Map [Analog Devices Wiki]), and I managed to understand which register is used for which propose. But your reference designs is streaming same data all the time, I need more advanced way of streaming data. So I need advice how to use your register to make these functions. Just to repeat again, to goal is to stream packet by packet of data, one after another. Please give me advice which steps I need to do to enable this communication. Also I did not understand what this part of code in test.c is performing (I know it is writing in registers, but for which propose).

 

 

if (PCORE_VERSION_MAJOR(hdl_version) > 7)
{
dac_write(ADI_REG_CHAN_CNTRL_7(0), 2);
dac_write(ADI_REG_CHAN_CNTRL_7(1), 2);
dac_write(ADI_REG_CNTRL_1, 0x0);
dac_write(ADI_REG_CNTRL_1, 0x1);
}
else
{
dac_write(ADI_REG_CNTRL_2, ADI_DATA_FORMAT | ADI_DATA_SEL(DATA_SEL_DMA));
dac_write(ADI_REG_CNTRL_1, 0x0);
dac_write(ADI_REG_CNTRL_1, 0x1);
}

Thank you in advance on answer,

Outcomes