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Question asked by willplatts on Feb 12, 2015
Latest reply on Feb 25, 2015 by charlyelkhoury



I am looking through the VHDL code for HDL AXI I2S. I am hoping to drive an SSM2518 from a Zynq device.


I am having trouble understanding a couple of things:


  1. In i2s_rx.vhd, if I have C_SLOT_WIDTH = 24. I have ‘bit_sync’ being asserted 24 times for each ‘channel_sync_int’, as I expect. ‘bit_sync’ is used to shift data into data_int (always 32 bits) from the LSB upwards. Therefore after 24 ‘bit_sync’s data_int(23:0) contain the correct data. However, on ‘channel_sync_int’, these bits are not registered into ‘data_latched’ (24 bits). Data_int(31:8) is latched into data_latched. Is this correct? Or should


data_latched(i) <= data_int(i)(31 downto 32 - C_SLOT_WIDTH);




data_latched(i) <= data_int(i)(C_SLOT_WIDTH-1 DOWNTO 0);


It seems quite deliberate, so perhaps I am missing some insight. (I have attached the process in question below)


  1. If C_NUM (number of channels) is set to 1, I assume this means 1 stereo channel? As this is how the I2S data seems to be read. If so, when this data is read over AXI, it is always from the same address, so how does the driver know if it is the left channel or right channel? Sorry if this is a simple question, I am not very familiar with Linux Device Drivers (audio or otherwise)


Many thanks in advance



Here is the whole process:

gen: for i in 0 to C_NUM - 1 generate



   unserialize_data: process(clk)


      if rising_edge(clk) then

         if reset_int then

            data_int(i) <= (others => '0');

         elsif bit_sync = '1' then

            if channel_sync = '1' then

               if sequencer_state = IDLE then

                  data_latched(i) <= data_int(i)(31 downto 32 - C_SLOT_WIDTH);

                  --data_latched(i) <= data_int(i)(31 downto 32 -

                  --C_SLOT_WIDTH + 8) &


               end if;

            end if;

            data_int(i) <= data_int(i)(30 downto 0) & sdata(i);

         end if;

      end if;

   end process unserialize_data;

end generate;