1) The data sheet is shown the effect of jitter of the input clock. (Page 22)
Does this mean the effects of jitter of the rising edge?
2) Jitter of the falling edge of the input clock signal will affect the performance of the ADC?
If it is correct, what are the effects?
3) Regard to the phase adjustment function of LVDS output clock:
Shift of 180 ° means that tDATA is a quarter of the DCO frequency as shown in Figure2?