My customer is using the AD9518-1.
Required Fout= 122.88Mhz on out4 (780mv) . The external Reference clk on REF1 is 25Mhz.
Currently it seems like the PLL is not working,
- 1. We get ~1.2Ghz from VCO + clocks on output0-5 depending on the dividers.
- 2. We can’t control the PLL by changing P, R, A, B dividers parameters
- 3. Turning the PLL on/Off (reg 0x10 = bits[1:0] = 2’b11/2’b00 . makes no change on output frequency.
Any scipt or registers settings file available?